QMCS 360 Class Notes # 17	Dr. Rick Smith Quantitative Methods and Computer Science
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Status on scheduling software

I/O Management - Chapter 11

Recap of I/O processing

Start with programmed I/O

Evolve to interrupt driven I/O

DMA reduces processor participation even more

Processor spends more time running applications, less time moving bits around

DMA Concept

DMA circuitry moves data from an I/O device directly to/from RAM

Interrupts processor when finished - to tell device driver to start another I/O operation

"Cycle stealing" of RAM or shared processor/RAM bus - but not necessarily

DMA Architectures

Single bus with "external" DMA devices

Single bus, integrate DMA into I/O interfaces

Option - have 2 or more devices hooked to a single DMA circuit

Separate I/O bus funnels through the DMA

IBM's "channels"

Dual-port RAM with I/O bus separate from processor bus

Eliminates "cycle stealing" more or less - may affect RAM timing

I/O Buffering

Issues, Goals

Read ahead of where the user will read next - overlap the DMA for the next input operation with the user's program execution

Collect data in RAM for writing out to HD when it's convenient and efficient - don't do lots of arbitrary writes, especially of partial blocks

Make it easy for device drivers to set up multiple operations and manage them

Ensure that the RAM is wired in - don't do I/O to paged or swapped memory

Unbuffered I/O

Trivial to implement

Trouble with paging/swapping

Trouble if user points to someone else's RAM for a DMA I/O operation

Single Buffer

Not too hard to implement

OS can allocate from unpaged RAM

No risk of transferring to unexpected RAM location

Problem: must move the data to the user's data space

Problem: no overlapping of I/O - must finish I/O and move data to user's space before the next I/O operation can happen

Performance:

T = time to input one block

C = compute time between block requests

M = time to move data from buffer to user's working RAM

without buffering, processing time = C + T

with a single buffer, time = max(C,T) + M

Double buffering - buffer swapping

Assign a pair of buffers to each "channel" of I/O (file, whatever)

I/O operation with one buffer overlaps the process of moving data between the user process the other buffer.

Once these operations are done, swap buffers and do another overlapped operation.

User never has to wait for I/O

If user program and I/O operations take same duration, both stay fully busy.

Performance:

Time = max(C,T)

If C<=T, I/O device is kept busy

If C>T, user process never has to wait.

Circular Buffering - "Multiple Exchange Buffering"

Lets hardware run closer to full speed by letting it do more I/O

More management overhead

The "bounded buffer problem" - not hard to solve.

Sounds more complicated than it is

Hardware - scatter gather I/O

Sophisticated DMA devices can manage queues of buffers for I/O

Give the device some I/O commands and a queue of buffers - it does the I/O using the available buffers.

Now what? File systems?